Focal plane arrays (FPAs) can be implemented with various known technology, such as charge-coupled devices, quantum well infrared photodetectors (QWIPs), or other such imaging devices. FPAs can be cooled, where they are configured with a Dewar cold finger or other cooling mechanism. Alternatively, an FPA can be uncooled (a common implementation is a microbolometer).
In any such cases, FPAs have either a digital or analog output. FPAs with digital outputs typically employ parallel CMOS busses to deliver the pixel data coming from the FPA to the array output, where the pixel data can then be processed as necessary (e.g., image formation and artifact removal). The same parallel CMOS bus structure is also used to deliver pertinent information to the FPA, such as pixel clocks, frame synchronization, and other control signals. There are a number of problems associated with such conventional interface structures.
For example, a parallel CMOS interface structure requires multiple digital I/Os or other such interfaces to the FPA, which adds complexity to the packaging and manufacturing process. Also, sensitive signals on the parallel CMOS interface are susceptible to digital crosstalk, electromagnetic interference (EMI), and other interferences. In addition, power dissipation associated with the parallel CMOS interface is signal dependent. As such, the power dissipation can vary substantially, thereby requiring additional design complexity as to power sources and management, as well as heat dissipation.
What is needed, therefore, are techniques for interfacing with FPAs. The interface techniques should be substantially unsusceptible to digital crosstalk and EMI, and should provide power dissipation that is signal-independent.